In the field of electronics, the planar metal-oxide-semiconductor (MOS) field effect transistor (FET) is widely used. In planar devices, the conductive channel that gives rise to device operation lies approximately parallel to the semiconductor surface on or in which the planar MOSFET is formed. As the fabrication technology has improved, there has been an ongoing effort to shrink the dimensions of the individual MOSFETs so that denser and more complex integrated circuits (ICs) can be fabricated. With the planar MOSFET, the gate length and corresponding induced source-drain channel length or spacing and uniformity are largely controlled by lithographic capabilities, for example, the lithographic images used to define the MOSFET gate and/or source-drain channel length. Unfortunately, lithography is rapidly approaching fundamental physical limitations so that it becomes more and more difficult to consistently and uniformly define small images and device elements such as the gate and source-drain channel length.
More recently, MOSFETs have been developed in which the field induced conductive channel is no longer limited substantially to the plane of the semiconductor surface, but extends into other dimensions. Fin-type FETs and trench-FETs are examples of such non-planar FETs. However, these non-planar FETs have limitations and problems of their own and so there is an ongoing need for further device structures and methods wherein the gate length and induced source-drain channel lengths of the MOSFETs are not dependent on lithographic capabilities or limitations but can be determined by other means independent of such lithographic limitations and which can still be fabricated using available processing capabilities.